Start of a thread on the TUHS mailing list mentioning the japanese project https://github.com/ryomuk/TangNanoDCJ11MEM/tree/main
Memory system and UART implemented on Tang Nano 20K FPGA for DEC DCJ11 PDP-11 Processor.
Sail is a language for defining the instruction-set architecture (ISA) semantics of processors: the architectural specification of the behaviour of machine instructions. Sail is an engineer-friendly language, much like earlier vendor pseudocode, but more precisely defined and with tooling to support a wide range of use-cases.
Found on the CHERI page https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/
A DECstation emulator on a business-card sized PCB. The description is a nice read. https://hackaday.io/project/196769-decstation2040 for a RP2040 version, with 32 MB HyperRAM, 1024 x 864 mono video, and USB mouse/kb