Start of a thread on the TUHS mailing list mentioning the japanese project https://github.com/ryomuk/TangNanoDCJ11MEM/tree/main
Memory system and UART implemented on Tang Nano 20K FPGA for DEC DCJ11 PDP-11 Processor.

A nontechnical reminiscence written in 1988 (on the occasion of unplugging Columbia University's last DECSYSTEM-20) for a Digital Press book that was to commemorate DEC's 36-bit machines with a series of articles, but was never published.

The project contains the VHDL code for a complete DEC PDP-11 system: a PDP-11/70 CPU with memory management unit, but without floating point unit, a complete set of mass storage peripherals (RK11/RK05, RL11/RL02, RK70/RP06, TM11/TU10) and a basic set of UNIBUS peripherals (DL11, LP11, PC11), and last but not least a cache and memory controllers for SRAM and PSRAM.

The design is FPGA proven, runs currently on Digilent Cmod A7 , Arty , Basys3 , Nexys4 DDR , Nexys4 , Nexys3 , Nexys2 and S3board boards. See section Complete Systems for more information.

5th Edition UNIX, 7th Edition UNIX, and 2.11BSD UNIX are known to boot, the hardware should also support DEC RT11 and RSX-11M, see section Running Systems for more information.

This is a retrocomputing project, rebuilding hardware from the late 70s and running historical software. To get into the tune see Figure D-1, a 11/70 console, and Figure F-2, a baseline system setup.

The Technical Reports appearing on this page were published by Compaq & DEC from 1981-2002.