The project contains the VHDL code for a complete DEC PDP-11 system: a PDP-11/70 CPU with memory management unit, but without floating point unit, a complete set of mass storage peripherals (RK11/RK05, RL11/RL02, RK70/RP06, TM11/TU10) and a basic set of UNIBUS peripherals (DL11, LP11, PC11), and last but not least a cache and memory controllers for SRAM and PSRAM.

The design is FPGA proven, runs currently on Digilent Cmod A7 , Arty , Basys3 , Nexys4 DDR , Nexys4 , Nexys3 , Nexys2 and S3board boards. See section Complete Systems for more information.

5th Edition UNIX, 7th Edition UNIX, and 2.11BSD UNIX are known to boot, the hardware should also support DEC RT11 and RSX-11M, see section Running Systems for more information.

This is a retrocomputing project, rebuilding hardware from the late 70s and running historical software. To get into the tune see Figure D-1, a 11/70 console, and Figure F-2, a baseline system setup.

A number of free tools for FPGA/ASIC EDA (e.g. Verilog to VHDL, Verilog to SystemC translators).

Design, VHDL code and software (assembler, compiler) for a Forth-oriented processor.

VHDL Mode is an Emacs major mode for editing VHDL code.