J1 is a small (200 lines of Verilog) stack-based CPU, intended for FPGAs. A complete J1 with 16Kbytes of RAM fits easily on a small Xilinx FPGA. Some highlights:
       Extremely high code density. A complete system including the TCP/IP stack fits in under 8K bytes.
       Single cycle call, zero cycle return
       Instruction set maps trivially to Forth
       Cross compiler runs on Windows, Mac and Unix
       Basic software includes a sizeable subset of ANS Forth and a portable TCP/IP networking stack.